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Google Israel

    דרושים Google Israel

    המשרות שלנו (37)
    תחום עיסוק
    חומרה / תוכנה
    כמות עובדים
    מעל 100
    שנת הקמה
    1998

    עוד עלינו

    משרות Google Israel

    הצעות עבודה
    מתוך 2
    נמצאו 15 משרות
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Lead coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
    Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
    Experience creating and using verification components and environments in standard verification methodology.

    Preferred qualifications:
    Masters degree in Electrical Engineering, Computer Science, or related field.
    Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
    Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113482
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.

    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
    Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
    Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
    Support emulation team members with debugging hardware, tooling, and project specific issues.
    Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
    Experience with associated Electronic Design Automation (EDA) tools, with automation and flow enhancements.
    Experience using command debug tools (e.g., Verdi, SimVision/Indago, GDB) and programming in C, C++, Perl, TCL, or Python.
    Experience with emulation systems, maintenance, upgrades, and methodology enhancements.

    Preferred qualifications:
    Master's degree in Computer Science, Electrical Engineering, or a related technical field.
    Experience deploying Electronic Design Automation (EDA) tools into distributed environments.
    Experience with system administration, networking, and security systems.
    Experience with Register-Transfer Level (RTL) design, Verilog, simulation, System Verilog, and assertions.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113537
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Plan the formal verification strategy and create the properties and constraints for digital design blocks.
    Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
    Contribute improvements to methodologies to enhance formal verification results.
    Architect and implement reusable formal verification components.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
    4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
    Experience capturing design specification in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)).

    Preferred qualifications:
    Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
    Experience working with one or more formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or Display and Video 360).
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113514
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a SERDES/PCIe Silicon Validation Engineer, you will take ownership on characterization of SERDES analog IPs provided by external vendors. Your job is to assure that the IP is meeting Google high standards. You will work closely with different multi-functional teams within the Silicon organization, as well as external vendors.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
    Write Inhouse tools/scripts to characterize the IP.
    Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
    Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
    Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
    5 years of experience working with PLLs, PCIe, SerDes IPs.
    Experience with lab automation software such as Python, and Matlab.
    Experience with SerDes Debug.
    Experience working with lab equipment such as Bidirectional Encoder Representations from Transformers (BERT), real-time scopes, Spectrum Analyzers, Vector Network Analyzers (VNA), or protocol analyzers.
    Experience with board design and debugging.

    Preferred qualifications:
    Experience in PCIe compliance measurements using high-end equipment (e.g., Analyzer, Exerciser).
    Experience in lab equipment for PCIe testing (physical or protocol level).
    Knowledge of Tx/Rx equalization techniques and adaptation.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113500
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Plan the formal verification strategy and create the properties and constraints for digital design blocks.
    Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
    Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
    Architect and implement reusable formal verification components.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
    8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
    Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).

    Preferred qualifications:
    Master's degree or PhD in Electrical Engineering or Computer Science, or a related technical field.
    Experience with scripting languages (e.g., Python).
    Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
    Knowledge of formal verification algorithms.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113497
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Junior SoC Design Verification Engineer, you will develop and execute efficient verification strategies ranging from planning and constrained random testing to debugging and closure while collaborating with engineers to validate digital designs across the life-cycle.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
    Responsibilities
    Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios.
    Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs using SVA and formal tools.
    Identify and define all relevant coverage measures to address design corner-cases.
    Debug tests with design engineers to ensure functionally correct design blocks.
    Close coverage gaps to identify verification holes and demonstrate progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
    1 year of experience with using verification components and environments in standard verification methodology.
    Experience verifying digital systems using standard Internet Protocol (IP) components/interconnects such as microprocessor cores, hierarchical memory subsystems.
    Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Array (FPGAs) or ASICs.

    Preferred qualifications:
    Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
    Experience with verification techniques and verification life-cycle.
    Experience with Application-specific integrated circuit (ASIC) standard interfaces and memory system architecture.
    Experience with performance verification of ASICs and ASIC components.
    .המשרה מיועדת לנשים ולגברים כאחד
     
    Show more...
    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113509
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Close coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    4 years of experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, throughput, security, and reliability.
    Experience in creating and using verification components and environments in standard verification methodology.

    Preferred qualifications:
    Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
    Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
    Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
    Experience with verification techniques, and the full verification life-cycle.
    Experience with performance verification of ASICs and ASIC components.
    Experience with ASIC standard interfaces and memory system architecture.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113515
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a Senior SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.

    As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
    Identify and write all types of coverage measures for corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Close coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    8 years of experience with creating and using verification components and environments in standard verification methodology.
    Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
    Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

    Preferred qualifications:
    Master's or PhD degree in Electrical Engineering.
    Experience with verification techniques, and the full verification life cycle.
    Experience with performance verification of ASICs and ASIC components.
    Experience with ASIC standard interfaces and memory system architecture.
    Experience in 4 or more SOC cycles.
    .המשרה מיועדת לנשים ולגברים כאחד
     
    Show more...
    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113512
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time and Entry Level Academic Jobs
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Apply close coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
    Experience creating and using verification components and environments in standard verification methodology.
    Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

    Preferred qualifications:
    Masters degree in Electrical Engineering or Computer Science.
    Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
    Experience with CPU implementation, assembly language, or compute SOCs.
    .המשרה מיועדת לנשים ולגברים כאחד
     
    Show more...
    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    113504
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
    Responsibilities
    Help to maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
    Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
    Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
    Support emulation team members in debugging hardware, tooling, and project specific issues.
    Help bring up external interfaces (e.g., USB, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms, and create test cases for tool issues encountered in the emulation compile and runtime flows.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    3 years of experience with emulation systems including maintenance, upgrades, methodology enhancements and Electronic Design Automation (EDA) tools (e.g., Palladium or Zebu).
    Experience with coding in Perl, TCL or Python.

    Preferred qualifications:
    Master's degree in Electrical Engineering.
    Experience in deploying EDA tools into distributed environments.
    Experience with system administration, networking, and security systems.
    Experience with Register-Transfer Level (RTL) design, Verilog, simulation (e.g., VCS, Incisive, Questa), System Verilog (e.g., DPI and transactors), and assertions.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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