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Google Israel

    דרושים Google Israel

    המשרות שלנו (26)
    תחום עיסוק
    חומרה / תוכנה
    כמות עובדים
    מעל 100
    שנת הקמה
    1998

    עוד עלינו

    משרות Google Israel

    הצעות עבודה
    מתוך 1
    נמצאו 7 משרות
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    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure.

    As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Lead coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    Experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
    Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
    Experience creating and using verification components and environments in standard verification methodology.

    Preferred qualifications:
    Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience.
    Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
    Familiar with CPU implementation, assembly language, or compute SOCs.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    עדכון קורות החיים לפני שליחה
    68702
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    As a Senior Hardware Emulation Engineer, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our ASIC projects. You will provide excellent emulation infrastructure and methodologies for supporting these projects. In this role, you will work directly with other emulation team members as well as designers, verification engineers, and software teams. You'll work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects.

    You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.
    Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

    Responsibilities
    Help maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
    Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
    Create tooling and automation to support emulation EDA tools, licensing, and job management in Google infrastructure.
    Support emulation team members with debugging hardware, tooling, and project specific issues.
    Help bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
    Experience with emulation systems, maintenance, upgrades, and methodology enhancements.
    Experience with associated EDA tools, and the addition of automation and flow enhancements.
    Experience using command debug tools (e.g., Verdi, SimVision/Indago, GDB) and programming in C, C++, Perl, TCL, or Python.

    Preferred qualifications:
    Master's degree in Computer Science, Electrical Engineering, or a related technical field.
    Experience deploying EDA tools into distributed environments and supporting their usage.
    Experience with system administration, networking, and security systems.
    Experience with RTL design, Verilog, simulation, System Verilog, and assertions.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    68711
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure.

    As part of our server chip design team, you will verify complex digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Close coverage measures to identify verification holes and show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
    Experience creating and using verification components and environments in standard verification methodology.
    Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

    Preferred qualifications:
    Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience.
    Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
    Knowledge of CPU implementation, assembly language or compute SoCs.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    68714
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    Our mission at Google System Infrastructure is to build high-performance computing System-on-a-Chip (SoC) for Google services and for Google Cloud customers, by solving real-world business challenges of performance, cost, and scale, utilizing unique hardware, software, and system solutions.

    As an SoC Debug and Monitoring Architect, you'll work closely with internal system teams and external customers to develop a comprehensive understanding of debug requirements as well as monitoring requirements and define methods and technologies to debug Googles SoCs and connect to the Cloud monitoring infrastructure. You will also work closely with the Engineering teams to drive the optimal balance between performance, features, power, schedule, and cost.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Work with Platform, Software, and CPU Architecture teams to define the debug, and monitoring of the custom core and implement ARM debug architecture features.
    Work with the Silicon Design teams to define the required debug features.
    Work on ARMs debug and monitoring philosophy and architecture, and configure it to Google SoC needs.
    Utilize ARM infrastructure to architect a solution for debug and monitoring.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Science or relevant technical field or equivalent practical experience.
    Candidates will typically have 5 years of experience with ARM Debug and Monitoring technologies
    Experience with architecting Debug and Monitoring solutions for CPUs or SOCs.

    Preferred qualifications:
    5 or more cycles of relevant industry experience (debug) with technical leadership.
    Experience with 5 or more cycles of SoC architecture and systems.
    Experience with 2 or more cycles of Servers SOC debug architecture.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    68700
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting and closing coverage.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Close coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
    Experience creating and using verification components and environments in standard verification methodology.
    Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

    Preferred qualifications:
    Masters degree in Electrical Engineering or Computer Science.
    Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
    Familiar with CPU implementation, assembly language or compute SOCs.
    .המשרה מיועדת לנשים ולגברים כאחד
     
    Show more...
    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    68718
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    In this role, you will take part in CPU development, leading the CPU architecture and microarchitecture definitions. You will collaborate with software and hardware architects, design, verification, and physical implementation teams. You will influence the building of processor performance analysis infrastructure with modeling, emulation, and silicon measurement and drive power and performance optimizations for our specific customers workloads.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Lead architectural definition of CPU core designs, facilitate and make final decisions.
    Participate in and influence the building of processor performance analysis infrastructure.
    Influence the development of architectural models with varying configurations across product categories.
    Perform Performance, Power, Area (PPA) trade-off analysis for architecture and microarchitecture features, communicate analysis results in both qualitative and quantitative fashion to support decisions.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
    Candidates will typically have 8 years of experience with microprocessor architecture and related technologies and algorithms.
    Experience with CPU architecture performance analysis, tools, and simulators at different abstraction levels (i.e., cycle accurate, functional, emulation).

    Preferred qualifications:
    Advanced degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
    Experience analyzing workloads and definitions of microarchitectural features.
    Knowledge of ARM architecture.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    הגשת מועמדות
    עדכון קורות החיים לפני שליחה
    68724
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    As an CPU Design Verification Lead, you will lead and drive complex technical projects from the concept/planning stage through execution and closure. As part of our server chip design team, you will verify complex digital designs, collaborate closely with design and verification engineers in active projects, and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification, and interacting with design engineers to identify important verification scenarios.
    Lead a team of chip engineers. Plan tasks, allocate people, and hold verification design/code reviews.
    Perform code development for critical verification features and capabilities.
    Work closely with system, software, design, and physical implementation stakeholders to make technical decisions and represent project status throughout the development process.
    Lead design verification efforts and work with external and internal partners.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    Candidates will typically have 8 years of experience with leading design verification teams through the full cycle from concept to delivery.
    Experience creating chip or subsystem design verification strategies and plans.
    Experience working with hardware verification languages (System Verilog/Specman), design verification methodologies (i.e. UVM), and chip design flow.

    Preferred qualifications:
    Masters degree in Electrical Engineering, Computer Science, or related field.
    Typically 15 years of experience in verification of complex IP/SoC/ASIC.
    Experience with ARM Instruction Set architecture or processor microarchitecture.
    Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
    Experience in design verification techniques including constrained-random simulation, formal property verification, or static verification.
    Experience in leading verification teams.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    עדכון קורות החיים לפני שליחה
    68707
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    מתוך 1