Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of Google's Server Chip Design team, you will verify complex digital designs and also collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting and closing coverage. You will help keep Google's networks up and running, ensuring users have the best and fast experience.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interact with design engineers to identify important verification scenarios.
Create and enhance random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Provide close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or Application-Specific Integrated Circuits (ASIC).
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores etc.).
Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Anycast Redirector Maglev (ARM) Instruction Set architecture or processor microarchitecture.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
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