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חברת השמה / כח אדם

לפני 2 שעות
דיאלוג
לחברת Start-Up המתמחה בפיתוח שבבים בעלי ארכיטקטורה מותאמת להרצת יישומי בינה מלאכותית ביעילות מרבית, דרוש/ה Silicon Validation engineer.
משרדי החברה נמצאים בקיסריה/תל אביב, ליד הרכבת, ומשלבים עבודה היברידית.
דרישות:
B.Sc. בהנדסת אלקטרוניקה/ הנדסת מכונות/ מדעי המחשב מאוניברסיטאות מובילות
5+ שנות ניסיון כ-VLSI or silicon Embedded SW engineer
ניסיון ב- C או ++ C
ניסיון עבודה בLinux המשרה מיועדת לנשים ולגברים כאחד.
 
עוד...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
67461
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
ביופרמקס
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה
לחברת הנדסה בינלאומית המתמחה בתכנון והקמת מפעלי פארמצבטיקה וביוטכנולוגיה,
דרוש /ה מהנדס /ת לתפקיד מגוון.
התפקיד כולל כתיבת פרוטוקולי ולידציה וביצוע ולידציות לציוד ומערכות הנדסיות בשטח, כולל מעקב רוחבי על פעילות תיקון.
דרישות:
מהנדס /ת מכונות /כימיה/ביוטכנולוגיה
ידע בקריאת שרטוטים - חובה.
אנגלית (קריאה וכתיבה) ברמה גבוהה - חובה.
שליטה מלאה ב Office- חובה.
ניסיון בתעשייה הפרמצבטית ובתעשייה הביוטכנולוגית - יתרון.
הכרות עם דרישות GMP - יתרון. המשרה מיועדת לנשים ולגברים כאחד.
 
עוד...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
24633
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
Familiar with CPU implementation, assembly language or compute SOCs.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
66430
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Our mission at Google System Infrastructure is to build the best cloud for Google services and for Google Cloud customers, by solving real world business challenges of performance, cost and scale, utilizing unique hardware, software, and system solutions. To better serve the rapidly evolving cloud needs, the team will develop custom chips for servers.


In this role, you'll perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of logic block and constraints on its input stimulus. You'll also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficulties to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience working on main interconnects, DMA, controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).

Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Knowledge of and experience working with one or more formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or 360-DV).
Understanding of formal verification algorithms.
Familiarity with CPU implementation, assembly language, or compute SOCs.
Proficiency with scripting languages (e.g. Python).
.המשרה מיועדת לנשים ולגברים כאחד
 
Show more...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
66386
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Take overall ownership of the Double Data Rate (DDR) controller validation, focusing on functional and performance validation.
Develop silicon validation drivers and tests to validate blocks functionality, integrated debug hooks, and performance monitors.
Support system ramp in debugging, integration of new Dual in-Line Memory Module (DIMM) vendors, and triage for Memory Controller (MC) related failures.
Requirements:
Minimum qualifications:
Bachelor's degree in Electronic Engineering or Computer Engineering, or equivalent practical experience.
Experience in embedded code development (e.g., C/C++).
Experience in DDR PHY/Controller post silicon validation activities.

Preferred qualifications:
Experience in DDR compliance measurements using high-end equipment (e.g., Oscilloscope, logic).
Experience with development in pre-silicon tools (e.g., Field Programmable Gate Array (FPGA), Emulator).
Knowledge of MC and DDR domain, system aspects, performance optimization, silicon bring-up, functional validation, and debug.
Knowledge of ARM based SoC architecture (e.g., Boot flow, memory allocation, etc.).
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
66405
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Collaborate with Design, Architecture, Process Technology, and Silicon Engineering teams to develop new product bring-up, verification, characterization, qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced manufacturing technologies.
Verify test solutions on pre-silicon models (simulation or emulation).
Develop and validate test programs on Automated Test Equipment (ATE) platforms in preparation for High Volume Manufacturing, working with ATE Vendor and internal cross-functional teams.
Support product sustain, including volume data analytics, test time and yield improvements, assess test escapees and Return Merchandise Authorization (RMA) returns, localize failures, implement containment measures in the manufacturing test flow, and partner with manufacturing, quality and reliability teams to implement root cause corrective actions.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Candidates will typically have 3 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
Experience in pre-silicon validation, test content generation/integration, and post-silicon enabling.
Experience in Python, Java, or C/C++.

Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience with CPU/GPU SoC architecture, design, validation, debug, and ASIC structural test frameworks (e.g., ATPG, BIST).
Experience developing or integrating manufacturing test hardware or software test methods.
Experience in hardware description languages and RTL debug.
Familiarity with Synopsys, Cadence, or Mentor verification platforms.
Ability to improve all aspects of post-silicon testing from definition to realization.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
66415
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Develop and execute tests in post-silicon validation, hardware emulators, and assist in bring-up processes from prototyping through post-silicon validation.
Drive to debug and investigate efforts on cross-functional issues, including pre-silicon prototyping platforms, post-silicon bring-up, and production.
Assist in operating and maintaining the hardware emulation platform for pre-silicon integration and validation. Ensure validation provides functional coverage for a design.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
Experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.
Experience with board schematics, layout, and debug methodologies using lab equipment.
Experience in functional tests for silicon validation (e.g., C, C++, or Python), or developing firmware, and embedded software.

Preferred qualifications:
Experience with hardware prototyping, including hardware/software integration (e.g., pre-silicon use of emulation, software-based test, and diagnostics development).
Experience with power characterization, Peripheral Component Interconnect express (PCIe) and Double Data Rate (DDR).
Experience with scripting (e.g., Python) for automation development.
Experience with ready to launch design, verification, or emulation.
Knowledge of System on a Chip (SoC) architecture, including boot flows.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
66418
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure.

As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
Familiar with CPU implementation, assembly language, or compute SOCs.
.המשרה מיועדת לנשים ולגברים כאחד
 
Show more...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
66401
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Cisco
Location: Tel Aviv-Yafo and Ofakim
Job Type: Full Time
What You'll Do

You'll be leading a team on our frontend design team at Cisco Silicon One team which is responsible for all chip design process from definition/micro architecture to product.

Our design engineers are dealing with all chip design aspect: Definition, Design, Verification, signoff, validation up to production.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.


Who You'll Work With

You'll be joining our Cisco Silicon One group which is the center of Ciscos ASIC design.


You'll be part of our Group driving our game-changing next-generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate


Our design center is very unique - hosting all silicon HW and SW development disciplines inside one site.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!
Requirements:
Who You Are

Experienced design/verification Engineer / team leader

B.Sc/M.Sc in EE from one of the top universities in Israel with a GPA above 85.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
65825
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As an SoC Design Verification Engineer, you will work as part of a Research and Development team, and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. Using your UVM and SystemVerilog coding and problem-solving skills, you'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting and closing coverage. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field of study, or equivalent practical experience.
Ability to communicate in English fluently.

Preferred qualifications:
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) and/or ASICs.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems)
.המשרה מיועדת לנשים ולגברים כאחד
 
Show more...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
66397
שירות זה פתוח ללקוחות VIP בלבד
משרות שנמחקו
ישנן 2 משרות במרכז אשר לא צויינה בעבורן עיר הצג אותן >