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Google Israel

    דרושים Google Israel

    המשרות שלנו (51)
    תחום עיסוק
    חומרה / תוכנה
    כמות עובדים
    מעל 100
    שנת הקמה
    1998

    עוד עלינו

    משרות Google Israel

    הצעות עבודה
    מתוך 2
    נמצאו 16 משרות
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    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    As a PCIe Silicon Validation Engineer, you will take ownership on characterization of SERializer/DESerializer (SERDES) analog IPs provided by external vendors. Your will assure that the IP is meeting Google standards. You will work with different multi-functional teams within Silicon organization, as well as external vendors.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
    Write Inhouse tools/scripts to characterize the IP.
    Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
    Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
    Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
    5 years of experience working with Phase-Locked Loops, PCIe, SerDes IPs.
    Experienced working with lab equipment such as Bidirectional Encoder Representations from Transformers (BERT), real-time scopes, Spectrum Analyzers, Vector Network Analyzers (VNA), or protocol analyzers.
    Experience with lab automation software such as Python, and Matlab.
    Experience with Serializer/Deserializer (SERDES) Debug.
    Experience of board design and debugging.

    Preferred qualifications:
    Experience in PCIe compliance measurements using high-end equipment (e.g., Analyzer, Exerciser).
    Experience in lab equipment for PCIe testing (physical or protocol level).
    Knowledge of Tx/Rx equalization techniques and adaptation.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    About the job
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your deep knowledge of Remote Direct Memory Access (RDMA) based transports.

    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
    Collaborate to develop new layer protocols for data center networking.
    Understand how everything interacts with software and other ASIC subsystems to implement data center networks.
    Define performance hardware/software interfaces. Write micro-architecture and design specifications.
    Define efficient micro-architecture and block partitioning/interfaces and flows.
    Requirements:
    Minimum qualifications:
    Bachelor's degree or equivalent practical experience.
    8 years of experience architecting networking ASICs from specification to production.
    Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
    Experience developing Register Transfer Level (RTL) for ASIC subsystems.
    Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

    Preferred qualifications:
    Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
    Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
    Experience working with software teams optimizing the hardware/software interface.
    Experience architecting networking switches, end points, and hardware offloads.
    Experience in a procedural programming language (e.g. C++, Python, Go.).
    Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102095
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    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
    Responsibilities
    Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Close coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASIC.
    Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
    Experience in creating and using verification components and environments in standard verification methodology.

    Preferred qualifications:
    Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
    Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
    Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
    Experience with verification techniques, and the full verification life cycle.
    Experience with performance verification of ASICs and ASIC components.
    Experience with ASIC standard interfaces and memory system architecture.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102102
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a Silicon Validation Lead at Google Cloud, you will validate Google's custom silicon solutions that power cloud infrastructure bringing the quality level. You will lead a team of engineers responsible for validating the functionality, performance, and power efficiency of chips designed specifically for Google Cloud services. Your knowledge in post-silicon validation will be essential in identifying and resolving issues before they impact the customers, ensuring a seamless and high-performance cloud experience.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Build and mentor a high-performing team of silicon validation engineers, and foster a culture of collaboration, innovation, and technical excellence.
    Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
    Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
    Lead the debug and resolution of silicon issues, collaborate with cross-functional teams such as design, architecture, software, and firmware.
    Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
    8 years of experience in silicon validation or a related field, with leading teams, and delivering successful projects.
    8 years of experience of silicon validation methodologies, tools, and techniques.

    Preferred qualifications:
    Experience with Field-Programmable Gate Array (FPGA) prototyping, emulation, or simulation platforms.
    Excellent written and verbal communication skills.
    Ability to convey technical concepts to audiences.
    Ability to lead and inspire technical teams, drive results, and build cross-functional relationships.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    עדכון קורות החיים לפני שליחה
    102107
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa
    Job Type: Full Time
    Our goal is to build a Google that looks like the world around us and we want Googlers to stay and grow when they join us. As part of our efforts to build a Google for everyone, we build diversity, equity, and inclusion into our work and we aim to cultivate a sense of belonging throughout the company.

    As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan, coordinate, and deliver custom silicon products.
    Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
    Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
    Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
    Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Computer Science, Electrical Engineering or equivalent practical experience.
    8 years of experience in program management.
    Experience in program management on technical cross-functional projects.
    Experience in one or more areas like architecture, design, verification, implementation, or validation with seven or more cycles of chip development.
    Experience in leading, developing and growing teams.

    Preferred qualifications:
    Master's degree or PhD in Engineering, or a related field.
    Experience as an engineer or manager in developing hardware or software systems around the chips.
    Experience with two or more chip cycles in a project management role with execution within resource and schedule constraints.
    Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners.
    Ability to motivate and focus a large collaboration to reach goals.
    Excellent communication and facilitation skills.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102110
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    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Merkaz
    Job Type: Full Time
    Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Googles needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.

    With your extensive technical expertise you take initiative to independently design and implement new systems, designing, implementing, and testing multiple features with little or no direction from tech lead or manager. You collaborate with key stakeholders to determine future direction of work.

    Google Cloud Storage is Google Cloud's scalable, distributed Object Store. As the actionable reliability team, we own the charter of improving the reliability of Google Cloud Storage (GCS) serving stack, with responsibilities in establishing accurate measurement of the serving stack health, designing mechanisms to discover production issues, building attribution frameworks to reduce the resolution time on production and customer-specific issues, and improving the reliability of the overall serving stack by optimizing the call pattern between the serving components.Google Cloud accelerates every organizations ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Googles cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.
    Responsibilities
    Set and communicate team priorities that support the broader organization's goals. Align strategy, processes, and decision-making across teams.
    Set clear expectations with individuals based on their level and role and aligned to the broader organization's goals. Meet regularly with individuals to discuss performance and development and provide feedback and coaching.
    Develop the mid-term technical goal and roadmap within the scope of our often multiple teams. Evolve the roadmap to meet anticipated future requirements and infrastructure needs.
    Design, guide and vet systems designs within the scope of the broader area, and write product or system development code to solve ambiguous problems.
    Review code developed by other engineers and provide feedback to ensure practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
    Requirements:
    Minimum qualifications:
    Bachelor's degree or equivalent practical experience.
    8 years of experience building and developing infrastructure or distributed systems.
    Experience with software development in one or more programming languages (e.g., Python, C, C++, Java, Javascript).
    Experience in a technical leadership role.

    Preferred qualifications:
    Masters degree or PhD in Engineering, Computer Science, or a related technical field.
    3 years of experience working in a matrixed organization.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102112
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
    Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
    Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
    Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
    Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
    8 years of experience in silicon validation or a related field.
    Experience in leading technical teams and build cross-functional relationships.
    Experience in silicon validation methodologies, tools, and techniques, including hardware setups, and automation tools on Emulation or FPGA platforms.

    Preferred qualifications:
    Experience with Field-Programmable Gate Array (FPGA) prototyping, Hardware Emulation (ZeBu Server, Palladium, Veloce), or simulation platforms.
    Knowledge of cloud computing technologies and architectures, including data centers, networking, and storage.
    Familiarity with hardware description languages (e.g., Verilog, VHDL) and hardware verification methodologies (e.g., UVM, SystemVerilog).
    Excellent communication skills, with the ability to convey technical concepts to diverse audiences.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102117
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a SoC Product Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing and mission-mode operation. You will work to support the machinery that goes into our data centers affecting Google users.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities:
    Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
    Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
    Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
    Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
    Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.
    Requirements:
    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
    8 years of experience in product engineering or test engineering.
    Experience with product engineering, supply chain data analytics, diagnostics for High Volume Manufacturing, or NPI.
    Experience with ATE and SLT.
    Experience in statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, Yield Explorer, JMP), or Python for data analytics.

    Preferred qualifications:
    Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
    12 years of experience in product engineering and test engineering.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    עדכון קורות החיים לפני שליחה
    102118
    שירות זה פתוח ללקוחות VIP בלבד
    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    Google System Infrastructure build the cloud for Google services and for Google Cloud customers, by solving world business test of performance, cost, and scale, utilizing unique hardware, software, and system solutions.The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
    We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

    Responsibilities
    Plan the verification of digital design blocks by understanding the design specification, and interacting with design engineers to identify important verification scenarios.
    Lead a team of chip engineers. Plan tasks, allocate people, and hold verification design/code reviews.
    Perform code development for critical verification features and capabilities.
    Work with system, software, design, and physical implementation stakeholders to make technical decisions and represent project status throughout the development process.
    Lead design verification efforts and work with external and internal partners.
    Requirements:
    Minimum qualifications:
    Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
    5 years of experience in technical leadership, leading project teams, or setting technical direction.
    Experience in managing Design Verification (DV) team.
    Experience in verification methodologies, tools, and techniques.
    Experience creating chip or subsystem design verification strategies and plans.

    Preferred qualifications:
    Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
    Experience with verification techniques, and full verification life cycle.
    Experience in verification of IP/SoC/ASIC.
    Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
    Experience with ARM instruction set architecture or processor microarchitecture.
    Experience in leading teams and delivering projects.
    .המשרה מיועדת לנשים ולגברים כאחד
     
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    102119
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    דיווח על תוכן לא הולם או מפלה
    מה השם שלך?
    תיאור
    שליחה
    תודה על שיתוף הפעולה
    מודים לך שלקחת חלק בשיפור התוכן שלנו :)
    Location: Haifa and Merkaz
    Job Type: Full Time
    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
    As a Executive CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities
    Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
    Identify and write all types of coverage measures for stimulus and corner-cases.
    Debug tests with design engineers to deliver functionally correct design blocks.
    Lead coverage measures to identify verification holes and to show progress towards tape-out.
    Requirements:
    Bachelor's degree in Electrical Engineering or equivalent practical experience.
    3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
    Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
    Experience creating and using verification components and environments in standard verification methodology.

    Preferred qualifications:
    Masters degree in Electrical Engineering or Computer Science.
    Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).
    Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
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