Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our server chip design team, you will use our Application Specific Integrated Circuit (ASIC) design experience to be part of a team that develops the ASIC SoC and SoC IPs from Power-On-Reset (POR) to Production. You will create SoC Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to Design flow and Methodologies.
In this role, you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testability (dft) etc. You will face technical issues and develop/define design options for performance, power and area.
The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/Block microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog).
Perform simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SOC-level.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with microarchitecture and specifications.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).
Preferred qualifications:
Experience with design sign off and quality tools (e.g., Lint, CDC, VCLP etc.).
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
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