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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 19 שעות
MICROSOFT ISRAEL
Job Type: Full Time
Microsoft is building the fastest and most reliable networks for cloud computing and for emerging workloads such as AI/ML. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsofts partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.

Our team has delivered Azure Boost and we are now looking for talented hardware verification engineers to join our team, developing Azures next generation networking devices.

Microsofts innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network.Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, and then deploy your work and see how it is used at cloud scale!

Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the worlds largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.

Responsibilities
Design test environments for units and full devices, based on deep understanding of customer requirements, DUT functionality, and system architecture.
Design and implement VIP, test benches, and verification infrastructure in SystemVerilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with hardware- and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.
Requirements:
6+ years of proven experience in verification of large ASIC/FPGA designs
Extensive knowledge of hardware verification concepts and tools (UVM, unit level and full chip verification, coverage-based verification)
A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.
Excellent communication skills in English.
BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.
.המשרה מיועדת לנשים ולגברים כאחד
 
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94937
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 21 שעות
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
93581
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 23 שעות
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The team's mission at Google System Infrastructure is to build cloud for Google services and for Google Cloud customers, by solving real world business challenges of performance, cost, and scale, utilizing unique hardware, software, and system solutions. In this role, you'll perform formal verification of design properties of ASIC designs. You will collaborate with design and verification engineers to define properties that capture the design intent of a logic block and constraints on its input stimulus. You'll also help define and improve design and verification methodologies that allow users to achieve formal verification closure.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities:
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).

Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Experience with scripting languages (e.g., Python).
Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
Knowledge of formal verification algorithms.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
93571
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow, with experience in using Cadence design tools.
Involve in implementing large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, demonstrate an understanding of associated issues and solutions.
Possess floorplanning, power grid design, and place-and-route methodologies, with expertise in using Synopsis tools like Floorplan Compiler (FC) and formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Possess scripting skills in Synopsis TCL, with expertise in Python.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience in Electronic Design Automation (EDA) tools and RTL2GDS flows.
Experience in the semiconductor/EDA industry.

Preferred qualifications:
Masters degree in Computer Engineering/Electronics Engineering.
Experience related to silicon quality or reliability.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
93587
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The team's mission at Google System Infrastructure is to build cloud for Google services and for Google Cloud customers, by solving real world business challenges of performance, cost, and scale, utilizing unique hardware, software, and system solutions. In this role, you'll perform formal verification of design properties of ASIC designs. You will collaborate with design and verification engineers to define properties that capture the design intent of a logic block and constraints on its input stimulus. You'll also help define and improve design and verification methodologies that allow users to achieve formal verification closure.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).

Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Experience with scripting languages (e.g., Python).
Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
Knowledge of formal verification algorithms.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
93578
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 

חברת השמה / כח אדם

1 ימים
לוגיקה IT
מיקום המשרה: מספר מקומות
לארגון ביטחוני מהגדולים בארץ ובחו"ל אשר משרדיו ממוקמים במרכז הארץ, דרוש/ה מהנדס/ת ציוד בדיקה ATE.
היקף המשרה: משרה מלאה וקבועה.
מיקום המשרה: תל אביב יפו, מחוז מרכז.
היברידיות: 100% מהמשרדים באופן קבוע אין אפשרות של עבודה מהבית.
דרכיי הגעה: קו רכבת ישראל, תחבורה ציבורית, כבישים מהירים.

תיאור המשרה
השתלבות בצוות העוסק בבניית אבני בניין חומרתיות העונות לאפיון בדיקתיות.
אפיון והטמעה של ארכיטקטורת החומרה במערכות בדיקה ATE.
עבודה עם כליי תכנון כגון: SolidWorks, OrCAD.
תכנון צמות ממשקים אלקטרוניים.
ניהול תהליכי פיתוח, סקרי תיכון, עבודה עם קבלני משנה, עלות והיבטי איכות הנדסית.
דרישות:
השכלה אקדמאית בהנדסת חשמל או אלקטרוניקה או אחר דומה חובה.
2 שנות ניסיון ומעלה בתפקיד של מהנדס/ת צב"דים ATE חובה.
ניסיון בכתיבה של Spec ו Sow כולל הגדרות לוחות זמנים וסיכום עליות לצב"ד חובה.
רקע או ניסיון עם הבנה מערכתית בתחום של אלקטרוניקה או מכניקה או תוכנה או קושחה יתרון.
רקע או ניסיון בליווי וניהול קבלני משנה מול הזמנות יתרון. המשרה מיועדת לנשים ולגברים כאחד.
 
עוד...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
95970
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 

חברת השמה / כח אדם

3 ימים
גב מערכות
מיקום המשרה: קיסריה
האם אתה מתעניין בטכנולוגיה רפואית?
אנחנו נלהבים לשפר תוצאות רפואיות ולעזור להציל חיים. המכשירים הרפואיים שלנו, התוכנה והשירותים המשויכים מתקדמים בכל העולם, ומשמשים לאבחון וטיפול במצבים קרדיו-רפואיים ורפואיים קשים.

?? תיאור התפקיד:
כחלק מהצוות שלנו, תתכנן, תעצב ותבצע בדיקות V V עבור תוכנה, חומרה ויישומים ניידים. תעבוד בצמוד עם צוותי R D, איכות ורגולציה כדי להבטיח עמידה בתקנים רפואיים.
דרישות:
3 ומעלה שנות ניסיון כמהנדס SQA ו/או V V
ניסיון בבדיקת מערכות משולב חומרה - תוכנה - קושחה
ניסיון בבדיקות מכשירים רפואיים
ידע בכלים כמו TestRail ו-JIRA
אנגלית ברמה גבוהה המשרה מיועדת לנשים ולגברים כאחד.
 
עוד...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
91569
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
3 ימים
Cisco
Location: Caesarea
Job Type: Full Time
You'll join the Front-End Design team at Cisco Silicon One, responsible for all chip design processes from definition and microarchitecture to final product.

Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.

We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

Who You'll Work With
You'll be part of our Cisco Silicon One group, the hub of Ciscos ASIC design.

As a member of our team, you'll contribute to driving our groundbreaking next-generation network devicesCisco Silicon One.

Our unique team operates in a startup atmosphere within a stable and leading corporation.

Our design center is exceptional, hosting all silicon hardware and software development disciplines under one roof.

We are redefining the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are crafted to be universally adaptable across service providers and web-scale markets, suitable for both fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a revolutionary, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, safer engine!
Requirements:
Minimum Requirements:
3+ years experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Advanced debug skills pre-silicon and in-lab
Preferred Requirements:
Scripting abilities
System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU)
Basic SW knowledge (chop driver level)
Basic design knowledge
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
92849
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Cisco
Location: Caesarea
Job Type: Full Time
You'll join the Front-End Design team at Cisco Silicon One, responsible for all chip design processes from definition and microarchitecture to final product.

Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.

We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

Who You'll Work With
You'll be part of our Cisco Silicon One group, the hub of Ciscos ASIC design.

As a member of our team, you'll contribute to driving our groundbreaking next-generation network devicesCisco Silicon One.

Our unique team operates in a startup atmosphere within a stable and leading corporation.

Our design center is exceptional, hosting all silicon hardware and software development disciplines under one roof.

We are redefining the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are crafted to be universally adaptable across service providers and web-scale markets, suitable for both fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a revolutionary, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, safer engine!
Requirements:
Minimum Requirements:
3+ years experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Advanced debug skills pre-silicon and in-lab
Preferred Requirements:
Scripting abilities
System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU)
Basic SW knowledge (chop driver level)
Basic design knowledge
.המשרה מיועדת לנשים ולגברים כאחד
 
Show more...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
92842
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
Cisco
Location: Caesarea
Job Type: Full Time
You'll join the Front-End Design team at Cisco Silicon One, responsible for all chip design processes from definition and microarchitecture to final product.

Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.

We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

Who You'll Work With
You'll be part of our Cisco Silicon One group, the hub of Ciscos ASIC design.

As a member of our team, you'll contribute to driving our groundbreaking next-generation network devicesCisco Silicon One.

Our unique team operates in a startup atmosphere within a stable and leading corporation.

Our design center is exceptional, hosting all silicon hardware and software development disciplines under one roof.

We are redefining the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are crafted to be universally adaptable across service providers and web-scale markets, suitable for both fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a revolutionary, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, safer engine!
Requirements:
Minimum Requirements:
3+ years experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Advanced debug skills pre-silicon and in-lab
Preferred Requirements:
Scripting abilities
System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU)
Basic SW knowledge (chop driver level)
Basic design knowledge
.המשרה מיועדת לנשים ולגברים כאחד
 
Show more...
הגשת מועמדות
עדכון קורות החיים לפני שליחה
92841
שירות זה פתוח ללקוחות VIP בלבד
משרות שנמחקו