לוח משרות דרושים בוגרי יחידות טכנולוגיות/אקדמיה בחיפה

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from POR to Production. Creating SoC Level micro architecture definitions, RTL coding and all RTL quality checks.
You will also have the opportunity to contribute to Design flow and Methodologies.

You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our server chip design team, you will use our Application Specific Integrated Circuit (ASIC) design experience to be part of a team that develops the ASIC SoC and SoC IPs from Power-On-Reset (POR) to Production. You will create SoC Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to Design flow and Methodologies.

In this role, you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testability (dft) etc. You will face technical issues and develop/define design options for performance, power and area.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/Block microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog).
Perform simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SOC-level.

Research happens at Google everyday, on many different embedded teams throughout the company. Our research reaches the user through both services and products such as Search, Maps, Google Assistant, Google Translate, Google Cloud, and our computing, storage, and networking infrastructure. To achieve this, were working on projects that utilize the latest technologies that push the boundaries of what is possible. At Google, research-focused engineering interns are embedded throughout the company, contributing to the setup of large-scale tests and deploying promising ideas quickly and broadly. Ideas may come from internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. From creating experiments and prototyping implementations to designing architectures, research-focused engineering interns work on real-world problems including artificial intelligence, data mining, natural language processing, hardware and software performance analysis, improving compilers for mobile platforms, as well as core search and more.

Google Research addresses challenges that define the technology of today and tomorrow. From conducting fundamental research to influencing product development, our research teams have the opportunity to impact technology used by billions of people every day.

Our teams aspire to make discoveries that impact everyone, and core to our approach is sharing our research and tools to fuel progress in the field -- we publish regularly in academic journals, release projects as open source, and apply research to Google products.

Responsibilities
Participate in research to develop solutions for real-world, large-scale problems.
Research, conceive, and develop software applications to extend and improve on Google's product offering.
Contribute to a wide variety of projects utilizing natural language processing, artificial intelligence, data compression, machine learning, and search technologies.

We have multiple positions open for Backend Software Engineers to be hired!!



Microsoft Azure Core ILDC (Microsoft Israel Development Center) team is a new and fast growing team, with multiple intriguing projects in different networking areas. Our team develops products spanning across all layers of the networking stack, from Field Programmable Gate Arrays (FPGA) offloading, through kernel drivers, Data Plane Development Kit (DPDK) applications up to user space code and more. Microsoft Azure is building the fastest and most secure networks in public cloud. ILDC (which is Microsoft Azures Israel Development Centers) is seeking candidates who ideally have networking and/or security background.


We are looking for excellent engineers who want to create, impact and collaborate with the best-in-class engineers. Be part of a growing team and contribute to its success. Innovate, solve problems and work as part of a team. Build network systems and services, taking products all the way from an idea to production. Join us as a Software Engineer to build the worlds fastest public cloud and make a difference to millions of people across the planet.

Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
You will develop Windows/Linux drivers, services and applications.

You will be participating in multidisciplinary projects in Microsoft, with our Hardware and OS partners.

You will collaborate with different partners in Azure Core team in Israel, US, India and Europe.

You will contribute to new feature design, implementation, testing and deployment at scale.