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What You'll Do
You'll be joining our Physical Design team within Cisco Silicon One, responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including:

Definition
Physical Synthesis
Place and Route
Optimization
Timing Closure
Design Floor Planning
We leverage the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Who You'll Work With
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devicesCisco Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.

Our design center is uniquely equipped, hosting all silicon hardware and software development disciplines under one roof.

We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a revolutionary, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!

Who We Are

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

What you will do

In this role, you will be responsible for Cisco SiliconOne Switch ASIC Post-Silicon Electrical Validation. You will deal with all chip validation aspects: Building validation plan, Coding the validation SW environment using Python and device SDK, test execution and results analysis. You will gain detailed knowledge of chip architecture, functionality and operation modes allowing you to debug and tackle Electrical chip related problems. Travel abroad for 2-4 weeks a year.

Who you will work with

You'll join our Cisco SiliconOne group, the center of Ciscos ASIC design. We are redefining the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products. As part of ASIC Hardware Engineering team located at San-Jose USA and at Caesarea Israel you will be cooperating with various groups across the globe such as: Board-Design, Software, Signal and Power Integrity, Packaging and Production.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead physical design of the CPU to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the System on a Chip (SoC) flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore Register-Transfer Level (RTL)/design tradeoffs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the team, and define physical design strategies and tactics to meet quality and schedule goals.