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2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with micro-architecture and solutions, and evaluate design options with performance, power, and area.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in reasoning design and debug with Design Verification (DV).

Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign off and quality tools (e.g. Clock Domain Crossing (CDC), etc.)
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced eXtensible Interface (AXI), ARM processors.
Knowledge of high performance and low power design techniques.
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משרות דומות שיכולות לעניין אותך
דיווח על תוכן לא הולם או מפלה
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Power Engineer in Google Cloud, you will be part of the server chip design team. You will work on Power related flows across the chip development end to end. You will have the opportunity to impact the Google Cloud Infrastructure, combine the latest innovations in algorithms and integrate circuits to create CPU SoC solutions for Google Cloud. You will partner with hardware, software, and data center controls teams to provide silicon and technology roadmaps.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools.
Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit).
Manage power delivery and packaging teams with simulations and scenario definitions.
Work intact with Architecture and DV to define power scenarios and tests, debug, and integrate into the flow.
Track whether power goals are met throughout execution.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field, or equivalent practical experience.
8 years of experience with power modeling, power delivery, and power distribution network/design.
Experience in power estimation and optimization flows and tools.
Experience with Vector based Physical Design Power Tools (e.g. PTPX Prime power).

Preferred qualifications:
Experience with power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, DVFS/AVS, etc.) and power management.
Experience with scripting languages (i.e., Python, Perl, TCL or Bash).
Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system (thermal mitigation and scheduling, cross-layer policy design).
Knowledge of system software components (i.e., Linux, drivers, runtime performance analysis, etc.).
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דיווח על תוכן לא הולם או מפלה
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שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Masters degree in Electrical Engineering, Computer Science, or related field.
Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Product Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing and mission-mode operation. You will work to support the machinery that goes into our data centers affecting Google users.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in product engineering or test engineering.
Experience with product engineering, supply chain data analytics, diagnostics for High Volume Manufacturing, or NPI.
Experience with ATE and SLT.
Experience in statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, Yield Explorer, JMP), or Python for data analytics.

Preferred qualifications:
Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
12 years of experience in product engineering and test engineering.
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Senior SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.

As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Preferred qualifications:
Master's or PhD degree in Electrical Engineering.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
Experience in 4 or more SOC cycles.
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107803
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Workload Analysis Researcher within Google Cloud's MSCA organization, you will be integral to developing silicon solutions powering Google's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the Google Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of Google users and Cloud customers.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Plan and execute detailed analysis of CPU workloads within the Google Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on Google Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.
Requirements:
Minimum qualifications:
PhD in Electrical and Electronics Engineering, or equivalent practical experience.
2 years of experience with software development in C++ programming language.
1 years of experience with data structures or algorithms.

Preferred qualifications:
Experience in performance modeling, performance analysis, and workload characterization.
Experience applying machine learning techniques and inference usage models on hardware.
Expertise in CPU architecture disciplines such as branch prediction, prefetching, value prediction, and caching policies.
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Google Israel
Location: Tel Aviv-Yafo
Job Type: Full Time and Entry Level Academic Jobs
Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Googles needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.

In this role, you will work with system teams and the Central Processing Unit (CPU) Architecture team to develop an understanding of the CPU, System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision-making. You will correlate performance projections with measured post-silicon data.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU architecture teams, SOC performance modeling team, and other Google Software teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
1 year of experience with software development in C++ programming language.
1 year of experience with data structures or algorithms.

Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Experience in modern CPU/ML architecture and micro-architecture.
Ability to learn coding languages as needed.
Excellent object-oriented, database design, and SQL skills.
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דיווח על תוכן לא הולם או מפלה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
חברה חסויה
Location: More than one
Job Type: Full Time and Hybrid work
Oversee weekly activities of the ATE team, ensuring effective management of day-to-day activities and coordination with other departments
Participate in annual and monthly planning for the department with the Engineering Manager
Design and develop TEST plans and TEST designs based on R D TEST requirements (including involvement in testability aspects for new products)
Development of automatic tests for production line, hardware, and software configurations and troubleshooting
Responsibility for documentation, technical instructions, SOW documents, ATP, etc.
Duplicate TEST tools (responsible for the whole process: purchasing, assembly, testing and release)
Responsibility for TEST tool development and support
Requirements:
Bachelors degree in electrical engineering or experienced Electrical Practical Engineer
At least 4 years of experience in developing automatic tests for the production line
2+ years of experience leading and managing a small team
Proven hardware design experience - OrCAD and Allegro preferred
Knowledge and experience in software development using LABVIEW - a significant advantage
High verbal and written communication ability in Hebrew and English
Personal skills: Ability to work independently or in a team of engineers, service-oriented, efficient, and task oriented
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חברת השמה / כח אדם

1 ימים
הרקלס גיוס השמה
Location: Haifa
Job Type: Full Time
This is a full-time on-site role for a software engineer, located in Haifa. The software engineer will be responsible for day-to-day tasks associated with software development, coding, testing, and debugging. The candidate will work in conjunction with the team to develop high-quality software with a focus on Embedded controllers for medical device systems.
Requirements:
Embedded CPU/MCU OS must
Proven experience in software development for at least 5 years must
Software development for medical devices products - must
PIC (Microchip) controllers development environment big advantage
Background in digital hardware - advantage
High/low-level control, drivers, and real time events handling advantage
C language
Establish and maintain methodologic design and documented code
Quick learner, analytical skills
Independent yet team player, interpersonal skills
Bachelor's or Master's degree in Computer Science or related field
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חברת השמה / כח אדם

2 ימים
דיאלוג
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה
חברת הייטק גלובלית המתעסקת באיכון בזמן אמת בתחום הHealthcare - בבתי חולים, קליניקות, בתי אבות ועוד.
מייצרים מעקב אחר מוצרים כולל ביצוע מוניטורניג של טמפרטורות וכו', כל האינפורמציה מגיעה ללקוח ודרכה יכול ללמוד על טיפול בחולים, טמפרטורות של תרופות וכו'.
כחלק מהתפקיד הצטרפות לצוות, עבודה מול גורמי פיתוח, קבלני יצור וגורמי יצור. ליווי היצור ועבודה מול קבלני משנה, הדרכות על מוצר חדש, כתיבת תיקי יצור ועוד. כפיפות לסמנכ"ל פיתוח.
כ350 עובדים, יושבים בפארק המדע עבודה מהמשרדים.
דרישות:
5 שנות ניסיון בהעברה מפיתוח ליצור
תואר בהנדסת אלקטרוניקה
ניסיון בעבודה מול גורמי פיתוח, קבלני יצור וגורמי יצור
ליווי יצור ועבודה מול קבלני משנה המשרה מיועדת לנשים ולגברים כאחד.
 
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דיווח על תוכן לא הולם או מפלה
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שליחה
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
אלביט מערכות
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה
לאתר החברה ביוקנעם דרוש.ה מהנדס.ת BOARD DESIGN לקבוצה העוסקת בפיתוח מוצרים בתחום היבשה
העבודה הינה החל משלב התכנון הראשוני עד לשלב האינטגרציה במערכת והעברה לייצור
דרישות:
תואר ראשון בהנדסת חשמל / אלקטרוניקה
ניסיון של 3 שנים לפחות בפיתוח
יכולת פיתוח עצמאית של כרטיס בכל שלבי הפיתוח השונים
ידע וניסיון בפיתוח FPGA- יתרון
ידע וניסיון בתחום הווידאו- יתרון
ניסיון בפיתוח מוצרים צבאיים יתרון
יכולת עבודה בצוות

*הפניה מיועדת לנשים וגברים כאחד
**רק פניות מתאימות יענו המשרה מיועדת לנשים ולגברים כאחד.
 
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