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Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

Site Reliability Engineering (SRE) combines software and systems engineering to build and run large-scale, massively distributed, fault-tolerant systems. SRE ensures that Google Cloud's servicesboth our internally critical and our externally-visible systemshave reliability, uptime appropriate to customer's needs and a fast rate of improvement. Additionally SREs will keep an ever-watchful eye on our systems capacity and performance.

Much of our software development focuses on optimizing existing systems, building infrastructure and eliminating work through automation. On the SRE team, youll have the opportunity to manage the complex challenges of scale which are unique to Google Cloud, while using your expertise in coding, algorithms, complexity analysis and large-scale system design. SRE's culture of diversity, intellectual curiosity, problem solving and openness is key to its success. Our organization brings together people with a wide variety of backgrounds, experiences and perspectives. We encourage them to collaborate, think big and take risks in a blame-free environment. We promote self-direction to work on meaningful projects, while we also strive to create an environment that provides the support and mentorship needed to learn and grow.


Responsibilities:
Improve the life-cycle of services from inception and design, through deployment, operation, and refinement.
Manage support services before they go live through activities such as system design consulting, developing software platforms and frameworks, capacity planning, and launch reviews.
Provide guidance to other team members on managing availability and performance of mission critical services, on building automation to prevent problem recurrence, and on building automated responses for non-exceptional service conditions.
Maintain services once they are live by measuring and monitoring availability, latency, and overall system health, and lead sustainable incident response.
Scale systems sustainably through mechanisms like automation and evolve systems by driving changes that improve reliability and velocity.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the DFT Senior Engineer, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project lifecycle, and providing sign-off DFT to tapeout.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.