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We seek a highly-skilled Technical Program Manager to join our dynamic team.

The ideal candidate will have a strong background in software engineering in the ASIC industry. This role requires a strategic thinker who can bridge the gap between hardware and software, ensuring seamless integration and program success.


Lead cross-functional teams to deliver complex ASIC projects on time and within budget.

Collaborate with software managers, product marketing, customers, and other stakeholders to define project scope, objectives, and deliverables.

Develop and maintain comprehensive project plans, schedules, and documentation.

Identify, assess, and mitigate project risks and issues.

Drive continuous improvement in the SW development and planning process.

Provide hands-on program management during all phases of silicon and SDK development from concept, design, pre and post Silicon development, validation, qualification, and production release phases.

Communicate effectively with all levels of the organization, from individual contributors to executive leadership and external customers.

Ensure alignment of the project objectives with organization goals/priority and customer needs.



Who You'll Work With

You'll join our Cisco Silicon One group, the center of Ciscos ASIC design.
You'll be part of our Group driving our game-changing next-generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate
Our unique design center hosts all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will lead a group of Hardware Engineers in an innovative and fast-paced environment with a focus on infrastructure for chip design. You will also lead technical projects from the concept/planning stage through execution and closure. You will help the team deliver designs that work. You will lead chip design process improvement projects in multiple areas of expertise.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Lead chip methodology Engineers to build and maintain a silicon design environment, support multi-geographic chip development teams, and also manage and mitigate support issues for tool flows.
Partner with Chip Project teams to define and standardize methodology across functional areas (e.g., Design, Design Verification, Physical Design).
Manage technical evaluations of tools for possible deployment, build and maintain relationships with partners.
Collaborate with teams across Google to identify and create opportunities for improved chip design across Google.
Participate in design reviews and track issue resolution and engage in technical and schedule trade-off discussions.