Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Design, develop, and maintain CAD tools and scripts to automate and streamline design tasks, verification processes, and data analysis.
Administer and optimize the front-end compute environment, ensuring reliability, performance, and scalability.
Provide technical support and training to Design and Verification teams on the use of CAD tools, scripts, and the compute environment.
Identify opportunities to enhance front-end development workflows, implement improvements, and document best practices.
Work closely with design, verification, and CAD teams to understand their needs, gather requirements, and deliver effective solutions.
Requirements: Minimum qualifications:
Bachelors degree or equivalent practical experience.
3 years of experience in coding or scripting languages (e.g., Python, TCL).
Experience with front-end design, verification, integration teams on tools development, maintenance, or support.
Preferred qualifications:
Experience in CPU or SoC design, debug, and verification flows.
Experience working with RTL teams and design integration methodologies that improve team productivity and velocity.
Experience with delivering chip design infrastructure or methodology including multi-HDL model builds and CI/CD systems.
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