Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Take overall ownership of the Peripheral Component Interconnect Express (PCIe) electrical testing and compliance testing.
Work with Silicon Validation and Platform teams on requirements, test definition, implementation and execution.
Support product ramp, integration of PCIe peripherals, and debug of PCIe related failures.
Develop and deliver tools to customers, for system level testing of the PCIe.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Candidates will typically have 5 years of experience with test and debug infrastructure or test/lab automation using scripting languages such as Perl, Python, or Tcl.
Experience in PCIe electrical validation and physical compliance such as setup, test flow, and results analysis.
Experience with industry debug tools and development of tests to root cause failures.
Experience in debugging PCIe physical related issues from silicon to system level.
Preferred qualifications:
Experience with embedded C/C++ development for silicon IPs/Subsystems, and/or scripting languages (e.g., Python).
Experience in lab equipment for PCIe testing (physical and/or protocol level).
Knowledge of ARM based SoC architecture (e.g., Boot flow, High-speed I/F initialization, memory allocation, etc.).
.המשרה מיועדת לנשים ולגברים כאחד