Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Microsoft is building the fastest and most reliable networks for cloud computing and for emerging workloads such as AI/ML. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsofts partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.

Our team has delivered Azure Boost and we are now looking for talented hardware verification engineers to join our team, developing Azures next generation networking devices.

Microsofts innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network.Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, and then deploy your work and see how it is used at cloud scale!

Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the worlds largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.