Senior Hardware Emulation Engineer, Networking, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Haifa and Tel Aviv-Yafo

Job Type: Full Time

In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-Specific Integrated Circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation-based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, supporting the hardware and lab bring up, and verifying our ASIC systems.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation EDA tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project-specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Requirements:
Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
Experience with associated EDA tools, automation, and flow enhancements.
Experience using command debug tools (e.g., Verdi, SimVision/Indago, GDB) and programming in C, C++, Perl, TCL, or Python.
Experience with emulation systems, maintenance, upgrades, and methodology enhancements.

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6 ימים

Senior Silicon DFT Lead

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Design For Test from DFT architecture to post silicon production support.
4 years of experience with people management.
Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the whole ASIC development flow.

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6 ימים

Physical Designer Engineer, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

Requirements:
Bachelors degree in Electrical Engineering or equivalent practical experience.
4 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.

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125578

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6 ימים

RTL Design Technical Lead, Networking, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

In this role, you will contribute in all phases of complex Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
8 years of experience in technical leadership.
Experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Experience developing RTL for ASIC subsystems.

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6 ימים

Senior SOC and IP Design Engineer, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).

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125622

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6 ימים

Senior Formal Verification Engineer, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Implement reusable formal verification components.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).

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125614

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6 ימים

RTL Design Engineer, Google Cloud

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience in logic design and debug with Design Verification (DV).
Experience with microarchitecture and specifications.

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125591

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חברת השמה / כח אדם

לפני 9 שעות

Senior Hardware Analog Engineer

חברה חסויה

Location: More than one

Job Type: Full Time and Hybrid work

We are searching for the best talent for an Senior Hardware Analog Engineer role, to join our team located in Yokneam, Israel.Purpose: The ideal candidate will have a strong background in analog circuit design, PCB layout, and electronic engineering principles.
This role involves designing, developing, and testing analog circuits for EP applications.
You will be responsible for:
Design and develop analog circuits, including amplifiers, filters, and power management systems.
Create and maintain schematic diagrams and PCB layouts using industry-standard software (OrCAD, PSPICE)
Collaborate with cross-functional teams to define design requirements and project specifications.
Conduct simulations and analyses to validate circuit performance and reliability.
Troubleshoot and resolve design issues during testing and production phases.

Requirements:
Bachelors degree in Electrical Engineering, Electronics, or a related field.
Minimum of 5 years of experience in analog board design.
Proficient in using circuit design and simulation tools (e.g., SPICE, Altium, Cadence).
Strong understanding of analog circuit theory and applications.
Experience with high-performance analog design and PCB layout techniques.
Excellent problem-solving skills and attention to detail.
Ability to work effectively in a collaborative team environment.
Knowledge of digital circuit design and mixed-signal systems.
Familiarity with regulatory standards and compliance for electronic products.
Experience with prototype development and testing methodologies.

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126488

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לעוד משרות ומידע על MICROSOFT ISRAEL >

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4 ימים

Hardware Engineer /Senior Hardware Engineer II (Multiple Roles) - Azure Core

MICROSOFT ISRAEL

תחום החברה :חומרה / תוכנה

מספר עובדים :מעל 100

כתובת החברה :תל אביב יפו

Location: Tel Aviv-Yafo

Job Type: Full Time

We're hiring for multiple roles for Logic Design Engineers, and Verification Engineers, on various levels, starting with 3 years of exprience

Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.

Requirements:
3+ years of proven experience in design and/or verification of large ASIC designs
Knowledge of hardware design and verification concepts and tools (e.g., timing, pipelined design, UVM, Specman, unit level and full chip verification, coverage-based verification, formal verification)
A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.
Excellent communication skills in English.
BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.

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125847

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חברת השמה / כח אדם

לפני 9 שעות

VLSI design engineer

חברה חסויה

Location: More than one

Job Type: Full Time and Hybrid work

Our group is responsible for the development of the company next generation SOC for AI Networking Compute. The development starts from product definition through architecture, design, verification and up to implementation.

The complex SOC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.

If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!

Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SOC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Advantages
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe - great advantage!
Leading VLSI teams/projects
Verification experience and knowledge with SV/UVM
CPU subsystem multi-core designs experience
Experience with Synthesis and STA analysis

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126511

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חברת השמה / כח אדם

לפני 9 שעות

FPGA Engineer

חברה חסויה

Location: More than one

Job Type: Full Time and Hybrid work

A medical device international company is searching for the best talent for a Principle FPGA Engineer role, to join our team located in Yokneam, Israel.
You will be responsible for:
Skilled FPGA design engineer as part of a small FPGA team
Implement DSP algorithms as well as high speed interfaces work closely with HW, software and system engineers.
FPGA design and architecture definition according to requirements.
Define, develop, and execute simulation environment and regression tests.
Take part in integration and system debug.

Requirements:
5-10 years of hands-on experience with FPGA design.
Bachelors degree Electronic engineering.
Deep understanding of FPGA development flow - End to end responsibility from architecture definition, design, simulation, and integration stages.
Familiarity with FPGA design tools for synthesis, timing analysis, and optimization.
Proficiency in FPGA design languages: Verilog, VHDL, and/or system Verilog.
system level understanding and debug capabilities.
Collaboration with cross-functional teams (software, HW and system engineers).

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126481

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