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As a Principal Engineer of Mixed-Signal Design within the Chip Innovation and Infrastructure team, you will help deliver products that have a substantive impact on Googles technical infrastructure. You will provide technical leadership to a group of silicon engineers in an innovative and fast-paced environment with a focus on mixed-signal design for machine-learning accelerators within Google data centers. This role has a significant component of cross-collaboration with cross-functional organizations. You'll bring out the best in the team to deliver designs that serve many of Googles core businesses.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Drive the mixed-signal design for CI2 in collaboration with other Google teams and external customers. Enable and maintain a strong co-design work process with all functions involved in designing and delivering mixed-signal components for CI2 products.
Ensure mixed-signal designs for CI2 chip architectures and fully enable and deliver Google product roadmap in terms of functionality, performance, power, cost, quality, usability, and deployability.
Set the direction for CI2 mixed-signal microarchitecture and modeling efforts and ensure on-time delivery of specifications to enable rapid and efficient development of next generation chips.
Collaborate with all functions of mixed-signal chip development (verification, implementation, etc.) and delivery (e.g., facilitate developers of various backgrounds to contribute to the mixed-signal architecture or encourage mixed-signal architects to be involved with chip development responsibilities).

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team works on the worlds toughest problems, redefining whats possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. Were at the center of amazing work at Google by being the flywheel that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services.

In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.


Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
Design and implement efficient power delivery networks (power grids) to ensure stable power to all parts of the chip.
Develop and validate high-performance, low-power clock networks (Clock Tree Synthesis - CTS) to ensure proper synchronization across the entire chip.
Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
Conduct extensive design rule checks (DRC) to ensure the layout adheres to manufacturing rules, performing layout versus schematic (LVS) checks to verify that the physical layout matches the logical design.