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Senior Hardware Engineer

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לפני 5 שעות
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience.
8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).
Experience with PCIe (PCI).

Preferred qualifications:
Experience in scripting languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of System-on-a-Chip (SoC) architecture.
Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
110623
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 5 שעות
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).

Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
110618
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 5 שעות
Google Israel
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will be responsible for performance analysis for an end-to-end networking stack using your infornation of RDMA based transports.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation, and defining and driving performance test plans.
Experience working with Software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
110641
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
אלביט מערכות
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה
לאתרי החברה ביוקנעם ורמת השרון דרוש.ה מהנדס.ת EMI / RFI
במסגרת התפקיד:
ליווי פיתוח מערכות ומוצרי האלקטרוניקה של החברה
ניתוח דרישות וכתיבת מענים למכרזים
ייצוג החברה בסקרים ובדיונים אל מול הלקוחות בארץ ובחו"ל
קביעת ארכיטקטורת הגנות EMI/RFI
ייעוץ ותכן מסננים ע"ג מעגלים מודפסים
כתיבת פרוצדורת בדיקה והובלת תהליך הבדיקה במעבדות השונות ובשטח
ביצוע סימולציות עבור מיגון, ברקים, אנטנות
ביצוע בדיקות חיים בצוותא
דרישות:
מהנדס.ת אלקטרוניקה עם 5 שנות ניסיון
ניסיון בתחום פיתוח פילטרים EMI/RFI והגנות ע"ג מעגלים מודפסי - יתרון
ניסיון בליווי עריכת מעגלים ובדיקת העריכות יתרון 
ניסיון בפיתוח ובדיקות בתחום ה RF יתרון משמעותי
היכרות עם תקני,464 461, 1275 - יתרון משמעותי
ניסיון בתוכנות סימולציה CST,FEKO יתרון
היכרות מעמיקה עם חומרה רלוונטית (קבלים, סלילים, טרנזורבים, רכיבי הגנה)


*הפניה מיועדת לנשים וגברים כאחד
**רק פניות מתאימות יענו המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
98184
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
3 ימים
Location: More than one
Job Type: Full Time and Hybrid work
A leading international company is looking for an R D
Job Description
Design and development of boards for Motion Control applications
Amplifiers
Power Supplies
High and low voltage circuits
Digital/Analog interfaces
Use advanced simulation tools to shorten the development cycle
Participate in the architecture design of future applications and requirements
Own safety and certification processes for analog and power boards
Support existing designs, implement changes and reliability improvement enhancements, TEST and validate new designs
Primary Duties and Responsibilities
Define Requirements, Specs and Interfaces, write Design, Spec and Validation documents
Design and develop Digital/Analog boards
Select major components, lead layout and placement using contractors
Perform Bring-Up tasks, validate design, support transition to manufacturing, support the boards i
Requirements:
B.Sc. in Electrical Engineering or a similar degree
Proven experience in designing power electronics
Excellent knowledge of relevant CAD and simulation tools
Experience with motion and control systems - advantage
Personal skills
Excellent interpersonal skills
Ability to work in a team of engineers in multi-disciplinary environment
Innovative and creative in solving complex problems
Fluent in English, both writing and speaking
Send your
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
110734
שירות זה פתוח ללקוחות VIP בלבד
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
6 ימים
MICROSOFT ISRAEL
Location: Haifa
Job Type: Full Time
Microsoft is building the fastest and most reliable networks for cloud computing and for emerging workloads such as AI/ML. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsofts partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.

Our team has delivered Azure Boost and we are now looking for talented hardware verification engineers to join our team, developing Azures next generation networking devices.

Microsofts innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, and then deploy your work and see how it is used at cloud scale!

Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the worlds largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.
Requirements:
We're hiring for multiple roles for Logic Design Engineers, and Verification Engineers, on various levels, starting with 3 years of exprience
3+ years of proven experience in design and/or verification of large ASIC designs
Extensive knowledge of hardware design and verification concepts and tools (e.g., timing, pipelined design, UVM, Specman, unit level and full chip verification, coverage-based verification, formal verification)
A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.
Excellent communication skills in English.
BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.
.המשרה מיועדת לנשים ולגברים כאחד
 
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הגשת מועמדות
עדכון קורות החיים לפני שליחה
109154
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