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Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

Youll be joining the post silicon validation team in PHY system group at Cisco Silicon One group as part of the silicon development at Cisco.

Our team deals with PHY and system aspects of the device: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the Automation Infrastructure and tools.

We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.



Who You'll Work With

You'll be part of our Group driving our game changing next generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation.

Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

You'll be joining our Hardware architecture team at Cisco Silicon One, focusing on advanced modeling and simulation using SystemC.
In this role, you'll contribute to the development of complex infrastructure of SystemC behavioral models.
Your work will enable the infrastructure to support the entire chip design process, enhancing simulation accuracy, performance, and cross-functional collaboration.


Who You'll Work With

Leaba Semiconductor, now part of Cisco, is the heart of Ciscos ASIC design group.
Youll be part of our team driving Cisco Silicon Ones next-generation network devices, working in a dynamic environment that combines startup agility with Cisco's corporate stability.
Our design center hosts all hardware and software development disciplines under one roof, enabling seamless collaboration and rapid innovation.
Together, we're building a unified, programmable silicon architecture foundational to Cisco's future routing products.

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

The Cisco Silicon One team develops breakthrough next-generation silicon products.

If you're looking to work with outstanding people, developing the first iteration of world-class products, join us!



In this role, you will:

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed


Who You'll Work With

You'll be joining Cisco Silicon One Israeli team which is the core center of Ciscos SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of Cisco silicon SW development and work with us to design and deliver breakthrough technologies.

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design networking hardware for enterprises and service providers of all sizes, as well as the public sector and non-profit organizations worldwide.

Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market, enabling customers to deploy best-of-breed silicon from Top-of-Rack (TOR) switches to web-scale data centers. This architecture supports service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and help shape Cisco's groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.

What You Will Do
In this role, you will be part of the Cisco Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.

Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

Who You Will Work With
Youll join our Cisco Silicon One group, the core of Ciscos ASIC design efforts.

We are redefining the industry by building a new internet for the 5G era, offering a unified, programmable silicon architecture foundational to all future Cisco routing products.
Based in Caesarea, Israel, youll collaborate with teams across the globe, including Board Design, Software, Signal and Power Integrity, Packaging, and Production groups.