לוח משרות דרושים מהנדס מחשבים במרכז

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with micro-architecture and solutions, and evaluate design options with performance, power, and area.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Product Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing and mission-mode operation. You will work to support the machinery that goes into our data centers affecting Google users.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.