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Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our server chip design team, you will use our Application Specific Integrated Circuit (ASIC) design experience to be part of a team that develops the ASIC SoC and SoC IPs from Power-On-Reset (POR) to Production. You will create SoC Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to Design flow and Methodologies.

In this role, you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testability (dft) etc. You will face technical issues and develop/define design options for performance, power and area.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/Block microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog).
Perform simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SOC-level.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

The Edge AI group is composed builds Agentic platform designed to support complex scenarios, including RAG. In addition, the group is building Video analysis at the edge and the cloud (Azure Video Indexer) that allows customers to get insights from videos at scale. Products involve cross team collaboration between product managers, data scientists and backend / full stack Engineers



We focus on creating real value for our customers by placing AI efficiently on top of video streams at scale and building a UX that allows organizations to explore, interact with their data and integrate the solution into their own systems.


Individuals in the team get a chance to impact the industry working across various areas, our data science team leads research and implementation of AI components, full stack developers work on cloud and edge technologies from the design until features arrive to the customer. Being at the center of innovation provides great opportunities for engineering excellence in an amazing work environment in a team that will allow you to develop, grow and contribute.
Responsibilities
As a developer, your code will reach Azure resources and extensions, and you will use various technology stacks with the latest tools and methodologies. You will be expected to break down problems, build execution plan, have open mind and eventually be accountable to your code all the way to production. Working in a multi-disciplinary team will require great communication skills and at the heart of it all, alignment with Microsoft values.

We have multiple positions open for Backend Software Engineers to be hired!!



Microsoft Azure Core ILDC (Microsoft Israel Development Center) team is a new and fast growing team, with multiple intriguing projects in different networking areas. Our team develops products spanning across all layers of the networking stack, from Field Programmable Gate Arrays (FPGA) offloading, through kernel drivers, Data Plane Development Kit (DPDK) applications up to user space code and more. Microsoft Azure is building the fastest and most secure networks in public cloud. ILDC (which is Microsoft Azures Israel Development Centers) is seeking candidates who ideally have networking and/or security background.


We are looking for excellent engineers who want to create, impact and collaborate with the best-in-class engineers. Be part of a growing team and contribute to its success. Innovate, solve problems and work as part of a team. Build network systems and services, taking products all the way from an idea to production. Join us as a Software Engineer to build the worlds fastest public cloud and make a difference to millions of people across the planet.

Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
You will develop Windows/Linux drivers, services and applications.

You will be participating in multidisciplinary projects in Microsoft, with our Hardware and OS partners.

You will collaborate with different partners in Azure Core team in Israel, US, India and Europe.

You will contribute to new feature design, implementation, testing and deployment at scale.

Microsoft is building the fastest and most reliable networks for cloud computing and for emerging workloads such as AI/ML. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsofts partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.

Our team has delivered Azure Boost and we are now looking for talented hardware verification engineers to join our team, developing Azures next generation networking devices.

Microsofts innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network.Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, and then deploy your work and see how it is used at cloud scale!

Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the worlds largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Static Timing Analysis, Design Floor Planning, Physical Verification.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Who You'll Work With
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.

As part of our team, youll give to the development of our next-generation network devices - Cisco Silicon One.
Our team operates in a startup-like environment within a stable and leading corporation.

Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.

We are revolutionizing the industry by building a new Ethernet, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!

Join the Cisco Silicon One PHY System Team, a key part of Ciscos silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.

Your responsibilities will include:

Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY sequences and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.

Who You'll Work With


You'll work within Cisco Silicon One, Ciscos ASIC design group, contributing to revolutionary network devicesCisco Silicon One.

Operate in a dynamic startup-like atmosphere within a stable and leading corporation.
Collaborate in a design center housing all silicon hardware and software development disciplines under one roof.
Be part of a team transforming the industry with a unified, programmable silicon architecture designed for 5G networks and beyond.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Cisco Silicon One group as part of the silicon development at Cisco.

Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.

We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Who You'll Work With
You'll be part of our Group driving our game changing next generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.

Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!