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Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Senior CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

Looking to take your low-level C++ skills to the next level and make a real security impact at scale? Join our Defender for Endpoint team in Israel!

Cyber-attacks are increasing in volume and sophistication, evading traditional defenses, and posing a growing risk to enterprises from outside criminal organizations and malicious insiders in the organization. The Microsoft 365 Defender suite leverages the Microsoft 365 security portfolio - including Microsoft Defender for Endpoint, Office, Cloud Apps and Identity, as well as Microsoft Sentinel and XDR - to automatically analyze threat data across domains, building a complete picture of each attack in a single dashboard to monitor, hunt, detect and remediate threats. With this breadth and depth of clarity defenders can now focus on critical threats and hunt for sophisticated breaches, trusting that the powerful automation in Microsoft's security products detects and stops attacks anywhere in the cyber-attack kill chains and returns the organization to a secure state. Join our team of engineers to develop cutting edge detection and remediation systems. Be a part of defining and shaping the next big leap in the product's journey.


Microsoft defender for endpoint EDR client team is developing the client agent (Sense) which responsible of collection evets from the endpoint, processing and sending to the cloud for analysis. The agent is deployed in over 100M machines, which sets MDE a high scale - high quality product.
Responsibilities
As a senior client engineer on our team, you will lead a squad of developers, developing Microsoft Defender for Endpoint's agent (Sense), using Cpp on Windows platform.
You will be working on cutting edge technologies to deliver exciting new features that impact and protect millions of users, with cross-team and cross-discipline collaboration (engineering, PM, design, research and data science).
You will work closely with experienced engineers and be part of an agile and fast-moving development team - and will have a role in mentoring your more junior peers and helping them succeed.
You will be expected to apply a critical view of our infrastructure, technologies and development process, proactively pushing to improve the product and our group

Microsoft is building the fastest and most reliable networks for cloud computing and for emerging workloads such as AI/ML. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsofts partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.

Our team has delivered Azure Boost and we are now looking for talented hardware verification engineers to join our team, developing Azures next generation networking devices.

Microsofts innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, and then deploy your work and see how it is used at cloud scale!

Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the worlds largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.