We are looking for a passionate and experienced Senior System Architect to join our Security team. This is a unique opportunity to lead the design of end-to-end security solutions that span across silicon, firmware, and OS layers. In this role, youll collaborate with diverse teams across the company, driving system-level thinking and delivering secure, scalable solutions. Were looking for someone who combines deep security expertise with strong system engineering instincts and the ability to influence and align across disciplines. If you're excited about redefining endpoint security in an AI-driven world, where new opportunities come with new threats, this is your chance to make a real impact. Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. We are committed to a diverse and inclusive workplace and strongly encourage applicants from all backgrounds and walks of life. Difference makes us better.

Responsibilities
Define and lead the architecture of security features across silicon, firmware, and OS layers

Translate product and customer requirements into clear system-level security specifications

Collaborate with cross-functional teams to design and deliver secure, scalable solutions

Develop system threat models and conduct security reviews to identify and mitigate risks

Drive alignment across engineering teams through clear documentation and technical leadership

Stay current with evolving security technologies, threats, and best practices

In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-Specific Integrated Circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation-based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, supporting the hardware and lab bring up, and verifying our ASIC systems.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation EDA tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project-specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

We're hiring for multiple roles for Logic Design Engineers, and Verification Engineers, on various levels, starting with 3 years of exprience



Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.