Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team defining solutions for network accelerations in data centers. You will have, multi-faceted responsibilities in areas such as project definition, with close collaborations with software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your knowledge of Remote Direct Memory Access (RDMA) and packet processors based transports.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Evaluate different silicon solutions for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Create high performance hardware/software interfaces.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Drive vendor execution in various engagements, standard component roadmaps, build to specification, and co-developments.
Participate in evaluation of future ASIC designs and general architecture.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience working in network architecture and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Experience in architecting RDMA or packet processor IPs across multiple generations.
Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience with TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
Experience working with software teams optimizing the hardware/software interface.
Proficiency in a procedural programming language (e.g., C++, Python, Go).
Knowledge of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
Ability to estimate performance by analysis, modeling, and network simulation, and define and drive performance test plans.
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