לוח משרות דרושים בוגרי יחידות טכנולוגיות/אקדמיה בתל אביב יפו

In this role, you will contribute in all phases of complex Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build an efficient and effective project timeline and work with the teams to make it reality.
Lead the creation of credible and data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the various team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams, balancing what is needed with what is possible.
Manage project execution and issues as they arise through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

As part of the GenAI Protect group at Check Point, youll join a pioneering team building cutting-edge security solutions for the new world of AI-driven workflows, and protect organizations from risks introduced by generative AI tools across browsers, desktops, and managed control points.

Youll play a critical role in designing and scaling the cloud infrastructure that powers GenAI Protect, ensuring reliability, performance, and secure operations at scale.
This position is ideal for an experienced DevOps engineer who thrives in fast-paced, innovation-driven environments and wants to shape Check Points next-generation security platform.

Key Responsibilities
Design, implement, and maintain CI/CD pipelines across multiple teams.
Architect secure, scalable infrastructure on AWS (EKS, ECS, EC2, RDS, CloudFront, IAM).
Automate provisioning using Terraform, CloudFormation, and GitOps.
Implement observability, logging, and alerting best practices (Prometheus, CloudWatch, ELK).
Drive reliability, scalability, and cost efficiency across environments.
Mentor engineers and establish DevOps culture and practices.

We are seeking an Experienced Senior DevOps Engineer to join our high-performing SaaS Security team.

Born from a successful cybersecurity startup acquisition, we operate as a dynamic team within a larger organization, driven by innovation and a passion for building cutting-edge security solutions.

As our lead DevOps engineer, you will build and maintain our large-scale, automated, SaaS infrastructure.

Our technology stack includes GCP, K8s, Prometheus, Terraform, PostgreSQL, Kafka, Temporal and Hasura. Youll work collaboratively with software engineering teams and tech leads, help automate and streamline our operations and processes and troubleshoot issues in our development, test and production environments.

Key Responsibilities
Design and develop our SaaS infrastructure, CI/CD pipelines, permissions model and deployment strategy.
Improve overall security posture, manage permissions and improve work processes.
Assist in introducing new technologies into group infrastructure.
Be a focal point for the stability of our infrastructure.

We use an interesting and mixed technology and services, we are mostly located in AWS but we have significant 3rd parties which we must manage their cost as well (like Datadog, Atlas, and more as examples).
In this position you will use your expertise in phyton and TF, you will have to perform automated actions and work on implementation with R&D of cost effective solutions.

Key Responsibilities
Design, build and manage our finops infrastructure in order to automatically reduce daily cost.
Get an experience with finops tools, develop dedicated processes, and have a great opportunity to grow and create impact.
Adapt and take on more responsibilities and own your share of the product.
Work with different RnD groups, business, and other teams at Check Point.