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What Youll Do: Join a team of curious, collaborative, and impact-driven security researchers. In this role, youll combine technical depth with creative problem-solving to protect millions of users and shape the future of identity security.

Analyze and understand the internals of authentication/network protocols and be able to independently reproduce identity-based attacks for investigation, study and research purposes.
Become a subject matter expert of investigation, collection, analysis and forensic of identity logs, including deep understanding of current trends and landscape of identity-based attacks and exploits
Collaborate with multiple product and engineering teams to design the next iteration of sensors, implement detection ideas and validate their effectiveness using a data-driven approach.
Work together with the different engineering teams to deliver the prototype and code to support the research findings.
Provide cybersecurity expertise as needed during security escalations and incidents to help protect Microsoft and our customers.

As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.