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Microsoft Azure Core ILDC (Microsoft Israel Development Center) team is a new and fast growing team, with multiple intriguing projects in different networking areas. Our team develops products spanning across all layers of the networking stack, from Field Programmable Gate Arrays (FPGA) offloading, through kernel drivers, Data Plane Development Kit (DPDK) applications up to user space code and more. Microsoft Azure is building the fastest and most secure networks in public cloud. ILDC (which is Microsoft Azures Israel Development Centers) is seeking candidates who ideally have networking and/or security background.


We are looking for excellent engineers who want to create, impact and collaborate with the best-in-class engineers. Be part of a growing team and contribute to its success. Innovate, solve problems and work as part of a team. Build network systems and services, taking products all the way from an idea to production. Join us as a Software Engineer to build the worlds fastest public cloud and make a difference to millions of people across the planet.

Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
You will develop Windows/Linux drivers, services and applications.

You will be participating in multidisciplinary projects in Microsoft, with our Hardware and OS partners.

You will collaborate with different partners in Azure Core team in Israel, US, India and Europe.

You will contribute to new feature design, implementation, testing and deployment at scale.

We are an agile team of technical engineers. Customer obsession is rooted deep in every decision we take. We move fast, allergic to over thinking and fail fast. We believe in building solutions the right way and with a do what it takes attitude. We are a team, a family, that will always succeed only as one team where all voices are heard, and all opinions are welcomed.  
Responsibilities


This is a broad cross-team role with high visibility. You will collaborate closely with multiple teams across Microsoft to deliver key customer solutions and the technology to support them.

- Lead end to end design, implementation and delivery of the future architecture for highly scalable, durable, low latency systems.

- Build an effective and agile development organization using industry leading best practices.

- Lead the definition of requirements, KPIs, priorities and planning of engineering deliverables.

- Proven team building experience as well as mentoring and growing team members.

We believe in enabling our team members to unlock their highest potential and invest a lot in building a collaborative and agile culture to achieve our business success. Join us and be part of our path to the next level of awesomeness!!

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. Creating SoC Level micro architecture definitions, RTL coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation or FPGA platforms.
Lead the debugging and resolution of silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Senior Design Verification Engineer, you will work as a part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.

In this role, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.